Journal Of Electrical Systems And Signals

Article 2, Volume 2, Issue 2, August 1393, Pages 1-10   

Document Type: Researsh Articles

DOI: 10.22067/ess.v2i2.35705

References

[1] C. C. Liu, S. J. Chang, G. Y. Huang and Y. Z. Lin, “A 10-bit 50-MS/s SARADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, pp. 731-740, Apr. 2010.

[2] H. Wei, C. H. Chan, U. F. Chio, S. W. Sin, U. Seng-Pan, R. Martins, and F. Maloberti, “A 0.024 mm2 8b 400MS/s SARADC with 2b/cycle and resistive DAC in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 188-190, Feb. 2011.

[3] Z. Cao, S. Yan, and Y. Li, “A 32 mW 1.25 GS/s 6b 2b/step SARADC in 0.13 µm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 542–543, Feb. 2008.

[4] P. Schvan, J. P. Bach, C. Fait, P. Flemke, R. Gibbins, Y. Greshishchev, N. Ben-Hamida, D. Pollex, J. Sitch, S. C. Wang, and J. Wolczanski, “A 24 GS/s 6b ADC in 90 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 544–634, Feb. 2008.

[5] Y. M. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S. C. Wang, “A 40 GS/s 6b ADC in 65 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 390-391, Feb. 2010.

[6] S. W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-µm CMOS,” IEEE J. Solid-State Circuits, vol. 41, pp. 2669-2680, Dec. 2006.

[7] J. Yang, T. L. Naing, and R. W. Brodersen, “A 1GS/s 6 bit 6.7 mW successive approximation ADC using asynchronous processing,” IEEE J. Solid-State Circuits, vol. 45, pp. 1469-1478, Aug. 2010.

[8] R. Sekimoto, A. Shikata, T. Kuroda, and H. Ishikuro, “A 40nm 50S/s–8MS/sultra-low voltage SARADC with timing optimized asynchronous clock generator,” in Proc. ESSCIRC, pp. 471-474, Sept. 2011.

[9] J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits. New Jersey: Prentice Hall, 2002.

[10] Z. Huang, A. Kurokawa, M. Hashimoto, T. Sato, M. Jiang, and Y. Inoue, “Modeling the overshooting effect for CMOS inverter delay analysisin nanometer technologies,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 29, pp. 250-260, Feb. 2010.

[11] C. H. Chan,Y. Zhu, U. F. Chio, S. W. Sin, Seng-Pan U, and R. P. Martins, “A voltage-controlled capacitance offset calibration technique for high resolution dynamic comparator,” in International SoC Des. Conf., pp. 392-395, Nov. 2009.

[12] Y. Xu, L. Belostotski, and J. W. Haslett, “Offset-corrected 5GHz CMOS dynamic comparator using bulk voltage trimming: Design and analysis,” in IEEE New Circuits Syst. Conf., pp. 277-280, Jun. 2011.

[13] B. W. Chen, J. P. Wang, and C. M. Tsai “A 3-GHz, 22-ps/dec dynamic comparator using negative resistance combined with input pair,” in IEEE Asia-Pacific Conf. Circuits Syst., pp. 648 - 651, Dec. 2010.

[14] L. Zhou, L. Liu, and D. M. Li, “A calibration technique for mismatch of capacitor arrays in A/D and D/A converter,” in Asia Pacific Conf. Postgraduate Research inMicroelectronics and Electronics, pp. 5-8, Oct. 2011.

[15] J. Y. Um, J. H. Kim, J. Y. Sim and H. J. Park, “Digital-domain calibration of split-capacitor DAC with no extra calibration DAC for a differential-type SARADC,” in IEEE Asian Solid-State Circuits Conf., pp. 77-80, Nov. 2011.

[16] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot, “A 12 fJ/conversion-step 8 bit 10 MS/s asynchronous SARADC for low energy radios,” in Proc. ESSCIRC, pp. 214-217, Sep. 2010.

[17] P. Harpe, Y. Zhang, G. Dolmans, K. Philips, and H. de Groot, “A 7-to-10 b 0-to-4 MS/s flexible SAR ADC with 6.5-to-16 fJ/conversion-step,” IEEE ISSCC Dig. Tech. Papers, pp. 472-474, Feb. 2012.

[18] K. Usami, M. Igarashi, F. Minami, T. Ishikawa, M. Kanzawa, M. Ichida, and K. Nogami, “Automated low-power technique exploiting multiple supply voltages applied to a media processor,” IEEE J. Solid-State Circuits, vol. 33, pp. 463 - 472, Mar. 1998.

[19] I. S. Jung, M. Onabajo, and Y. B. Kim, “A10-bit 64MS/s SARADC using variable clock period method,” in IEEE International Midwest Symp. Circuits Syst., pp. 1144-1147, Aug. 2013.

[20] C. Y. Liou and C. C. Hsieh, “A 2.4-to-5.2 fJ/conversion-step 10 b 0.5-to-4 MS/s SAR ADC with charge-average switching DAC in 90 nm CMOS,” in IEEE ISSCC Dig. Tech. Papers, pp. 280-281, Feb. 2013.

[21] A. Shikata, R. Sekimoto, T. Kuroda, and H. Ishikuro, “A

0.5 V 1.1 MS/sec 6.3 fJ/conversion-step SAR-ADC with tri-level comparator in 40 nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, pp. 1022-1030, Apr. 2012.

[22]D. Zhang, A. Bhide, and A. Alvandpour, “A 53-nW 9.1-ENOB 1-kS/s SAR ADC in 0.13-µm CMOS for medical implant devices,” in IEEE J. Solid-State Circuits, vol. 47, pp. 1585-1593, April 2012.